Ballistic deflection transistors are among the ways that researchers hope to speed up processors.
“What we're talking about is scaling though parallelism, rather than through frequency (Hertz),” Koehl says. “So while the chip may be running at 3.1 GHz, due to the fact that we have so many cores operating in parallel, it's possible to achieve Tera-scale performance. In this case, ‘Tera-' refers to computational abilities of the chip (TeraFLOPs) and the amount of data it can move about (Terabytes).”
Like the University of Rochester's ballistic deflection transistor, Intel's TeraFLOP designs are still a long way from commercial availability.
“We expect to enter the tera-scale era for general purpose microprocessors in the next five to 10 years,” Koehl says. “The reason we're doing so much research is that scaling via parallel computing is fundamentally different than scaling by speeding up serial processing. There are many challenges to be addressed to make these processors scalable, adaptable, reliable, and programmable.”
One of those challenges goes back to the whole reason for doing this kind of research: the applications. In pro AV, it's not difficult to think of applications that could leverage faster processors to provide a better or richer user experience.
“The software must scale with the hardware,” Koehl says. “In other words, we must enable new applications that can put this vast amount of computing capability to best use for people: enabling virtual worlds and machine learning, for instance. At the same time, we must work with industry and academia to make parallel programming for highly-threaded software much easier than it is today, including new languages, operating systems, abstraction layers, and hardware techniques.”ONLINE RESOURCES
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Tim Kridel is a freelance writer and analyst who covers telecom and technology. He's based in Kansas City and can be reached at firstname.lastname@example.org.